Senior Physical Design Engineer

About the role

We are looking for a Senior Physical Design Engineer to lead full‑chip and block‑level physical design projects on advanced technology nodes (10nm and below). You will own the end‑to‑end flow from floorplanning to tape‑out, ensuring high‑performance, low‑power silicon.

Key responsibilities

• Develop deep floorplans, partition budgets, power mesh distribution and clock‑tree synthesis.
• Perform placement, clock‑tree routing, CTS, and full place‑and‑route.
• Lead timing closure activities, including sign‑off, signal‑integrity and noise analysis.
• Execute ECOs for functional and timing fixes.
• Run validation and qualification checks: formal verification, EM/IR, DRC, LVS, antenna and ERC analysis.
• Contribute to low‑power solution development and implementation.
• Write and maintain scripts for clock‑skew, critical‑path and IO constraint analysis.

Required profile

• 8+ years of RTL‑to‑GDSII experience on 10nm or smaller nodes with designs of 500k‑1M+ instances.
• Strong background in floorplanning, power planning, CTS, placement, routing and timing closure.
• Proficiency in Synopsys and/or Cadence PnR and timing tools.
• Hands‑on experience with sign‑off tape‑out flow and ECO generation.
• Ability to work independently on multiple high‑complexity design cycles.

Required skills

• Synopsys and Cadence physical‑design tools
• Timing analysis (STA/PTSI) and signal‑integrity closure
• EM/IR, DRC, LVS, ERC analysis and fixing
• Perl, TCL, Python scripting and Makefile usage
• DFT scan insertion, coverage and optimization
• Power‑grid planning and clock‑tree synthesis

What we offer

• Competitive salary and benefits
• Respect for work‑life balance and personal choices
• All necessary tools for high‑performance engineering
• Long‑term stability and responsible career growth