Senior FPGA based SoC Prototyping Engineer

About the role

Join U‑Blox’s SoC Verification team as a Senior FPGA based SoC Prototyping Engineer. You will bridge the gap between design and firmware groups, delivering functional FPGA prototypes that accelerate early firmware development and shorten time‑to‑market for GNSS SoC products.

Key responsibilities

• Define and own the FPGA‑based SoC prototyping strategy, including hardware setup and validation.
• Port ASIC RTL to FPGA‑friendly, synthesizable RTL, handling floorplanning, constraints, and verification through simulation and lab testing.
• Coordinate with design and firmware teams to deliver on‑time functional prototype versions.
• Continuously improve internal FPGA prototyping flows, verification methodology, and back‑end processes.
• Support hardware/firmware bring‑up, troubleshoot issues, and assist prototype users.

Required profile

• Proven experience delivering full‑SoC FPGA prototypes for low‑power ASIC/SoC projects.
• Hands‑on expertise with AMD Ultrascale+ and Altera FPGA families.
• Strong background in ASIC design concepts (architecture, clock tree, verification, modeling).
• Problem‑solving mindset, proactive attitude, and detail‑oriented approach.

Required skills

• AMD Ultrascale+ FPGA
• Altera (Intel) FPGA
• RTL development and synthesis
• Floorplanning and timing constraints
• Simulation and lab verification
• Hardware bring‑up and troubleshooting
• ASIC architecture and clock‑tree design
• Low‑power SoC prototyping

What we offer

• Full‑time hybrid work model (Thalwil, Leuven or Athens)
• Opportunity to influence cutting‑edge GNSS SoC products
• Flat, collaborative team environment with room for individual initiative
• Equal‑opportunity workplace