Senior Digital Verification Engineer

About the role

Renesas Electronics is looking for an experienced Senior Digital Verification Engineer to lead end-to-end verification of complex IC blocks and systems. The role sits in Kallithea, Athens, and involves defining verification strategy, driving coverage to closure and collaborating with global architecture, design and software teams.

Key responsibilities

• Architect and execute comprehensive verification strategies, test plans and UVM-based environments built from scratch
• Drive functional and code coverage to closure using constrained-random testing, assertion-based verification (SVA) and formal methods
• Review design specifications early in the cycle to improve their quality and fitness for verification
• Partner with global architecture, design and software teams to optimise hardware/software partitioning and system-level verification
• Mentor and tutor junior engineers, champion design and verification reviews and optimise automation flows for reusability and performance
• Evaluate third-party VIP and tools and steer make/buy decisions for maximum engineering efficiency

Required profile

• Extensive proven experience in ASIC/IC digital verification
• Ability to set up a UVM testbench from scratch and turn a specification into a complete verification environment
• Intermediate to advanced digital design skills
• Excellent interpersonal skills and strong written and spoken English

Required skills

• SystemVerilog and UVM
• Cadence Xcelium and eManager/vManager
• Verilog and VHDL
• Functional verification, assertion-based verification, formal verification and regression frameworks