Senior Digital Designer (RTL & Microarchitecture)

About the role

We are looking for a Senior Digital Designer to lead the development of functional specifications and micro‑architecture for high‑performance digital blocks in advanced semiconductor products. The role combines RTL design, debugging, and collaboration with verification and physical design teams.

Key responsibilities

• Lead functional specification development for complex digital systems.
• Design and implement micro‑architecture (uArch) for high‑performance blocks.
• Perform RTL debugging to ensure design correctness and efficiency.
• Run and analyze lint and clock‑domain‑crossing (CDC) checks.
• Collaborate with verification, physical design, and architecture teams.
• Contribute to front‑end synthesis and optimization (bonus).
• Apply power‑optimization techniques for energy‑efficient designs.

Required profile

• 7+ years of hands‑on digital design experience.
• Strong knowledge of Verilog and/or VHDL; SystemVerilog a plus.
• Experience with Cadence Genus, Synopsys Design Compiler or Fusion Compiler is a plus.
• Proven expertise in RTL design, micro‑architecture development, and functional specifications.
• Deep understanding of linting tools, CDC methodologies, and debugging flows.
• Bachelor’s degree in EE, ECE, CE, CS or related field; MS/PhD highly desired.
• Excellent communication and teamwork skills.

Required skills

• Verilog
• VHDL
• SystemVerilog
• Cadence Genus
• Synopsys Design Compiler
• Fusion Compiler
• RTL design
• Micro‑architecture development
• Functional specification
• Linting tools
• CDC analysis
• Front‑end synthesis
• Power optimization
• SoC integration

What we offer

• Work on innovative semiconductor products with real‑world impact.
• Collaborative, forward‑thinking engineering team.
• Flexible work environment and competitive compensation.
• Opportunities for technical leadership and career growth.